Method of Dicing a Wafer

ABSTRACT

A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface.

This is a continuation application of U.S. application Ser. No.13/029,984, entitled “Method of Dicing a Wafer” which was filed on Feb.17, 2011 and is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to device processing and inparticular embodiments to a method of dicing a wafer.

BACKGROUND

Some embodiments according to the invention are related to a method ofdicing a semiconductor wafer. Some embodiments according to theinvention are related to a wafer as an intermediate product during themethod of dicing the wafer. Some embodiments according to the inventionare related to a semiconductor device obtained from the method of dicinga wafer.

The semiconductor integrated circuits (or devices, or chips) that aremanufactured on wafers typically need to be kept apart from each otherby a given distance. This distance is called dicing street, scribe-line,kerf, dicing channel, etc.

This distance is needed so that the singulation process that is normallybased on a disruptive mechanical sawing process can be performed withoutdamaging the circuits. The sawing process is normally conducted by meansof a rotating diamond circular blade. In recent times, a prescribingprocess assisted by an ablation laser is utilized. The kerf, whichsurrounds each chip on its four sides has a width which varies fromtechnology to technology. By making use of conventional blade dicing andtaking into account the stringent manufacturing quality and reliabilityrequirements of today's mass production standards (e.g., Zero DefectPolicies), the narrowest available kerf released in production appearsto be approximately 62 μm wide.

The area required for the kerf is typically destroyed during the dicingprocess. For this reason, temporary structures may often be found in thekerf area. For example, within the space of the kerf, a number ofstructures necessary to control the manufacturing operations may beplaced. Such structures comprise the typical process control monitorelectrical test structures (PCM), the photolithographic alignmentstructures, the wafer level reliability test circuits, the filmthickness and critical dimension (CD) measurement structures, etc. Whenthe mechanical rotating blade-assisted dicing operation is performed,the wafer state of the kerf is wasted and mentioned test structures aredestroyed. The width of the kerf is essentially determined by thefollowing factors: The width of the dicing blade, the width of the testand measurement structures plus margins for quality and reliabilityconcerns.

When making use of mechanical rotating blade-assisted dicing, thefollowing observations can typically be made:

The smaller the area of the chip, the higher the percentage of wafermaterial wasted in the kerf.

The edges of the singulated die are particularly rough and there is ahigh risk of chipping of the upper films of the chip.

Micro-cracks can be easily generated which propagate within theintegrated circuit (which can pose reliability constraints);consequently, the integrated circuit has to be protected from crackissues by means of “crack stop” structures, which, in turn, increase thechip area.

Generation of wafer dust (generally silicon) that can lead todiscoloration/corrosion of the input/output circuit pads (generally madeof aluminum).

The utilization of water, intended to cool down the blade and wash outthe dirt, can lead to corrosion of the aluminum of the pad.

The dicing has to be performed along perpendicular and/or rectangularkerf lines.

During the last few years, a new sawing/dicing technology has emerged inthe industry, known as Stealth Dicing, which relies on a laser beam toperform the singulation of the dies. The main characteristic of such aStealth Dicing technology is that the laser beam is focused at aselectable depth within the bulk of the wafer. The energy carried by thelaser beam is therefore capable of locally modifying the morphology ofthe crystalline wafer (e.g., silicon, GaAa, etc.) from mono-crystallineto poly-crystalline. As a result, a precisely localized line ofmechanical stress is introduced within the bulk of the wafer at theselected depth. Once the wafer has been processed through the StealthDicing tool, it is still not yet singulated. In order to separate eachdie from its neighbor, it is necessary to apply a controlled mechanicalexpansion of the wafer; such an operation is performed in a separatemodule of the Stealth Dicing machine called expander.

SUMMARY OF THE INVENTION

A method of dicing a semiconductor wafer according to the teachingsdisclosed herein comprises forming a layer stack on a first main surfaceof a substrate. The layer stack is etched and a portion of the substrateaccording to a pattern defining an intended dicing location to obtain atrench structure. The substrate is irradiated with a laser-beam tolocally modify the substrate between the bottom of the trench structureand the second main surface of the substrate opposite to the first mainsurface.

In another embodiment according to the teachings disclosed herein, amethod of dicing a semiconductor wafer comprises forming a layer stackon a first main surface of a substrate. The layer stack comprises ametal region at an intended lateral dicing location and a finalpassivation layer. A photoresist layer is formed on the finalpassivation layer. A photolithographic process is performed toselectively remove the photoresist layer at a location that issubstantially laterally aligned to the metal region. The finalpassivation layer is etched at the location that is substantiallylaterally aligned to the metal region. The metal region of the layerstack is etched to expose the first main surface of the substrate at theintended lateral dicing location. The substrate is etched through anopening in the layer stack obtained during the etching of the metalregion to obtain a trench structure in the substrate. The substrate isirradiated with a laser beam to locally modify the substrate between abottom of the trench structure and a second main surface of thesubstrate opposite to the first main surface. Individual chips aresingulated from the wafer.

In another embodiment according to the teachings disclosed herein awafer comprises a substrate, a layer stack arranged on a first mainsurface of the substrate, a trench structure in the layer stack and in aportion of the substrate, and a modified substrate region locatedbetween a bottom of the trench structure and a second main surface ofthe substrate. The layer stack may comprise at least one conductiveinterconnection layer. The trench structure may act as a boundary of atleast one chip region of the wafer.

Another embodiment according to the teachings disclosed herein providesa semiconductor device comprising a substrate, a layer stack, and amodified substrate region. The substrate comprises a first main surface,a second main surface opposite to the first main surface, and a lateralsubstrate surface. The layer stack is arranged on the first main surfaceof the substrate and comprises a lateral layer stack surface. Thelateral layer stack surface is aligned to the lateral substrate surface.The modified substrate region is located at the lateral substratesurface between the first main surface and the second main surface.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the embodiments of the teachings disclosed herein willbe more readily appreciated and better understood by reference to thefollowing detailed description, which should be considered withreference to the accompanying drawings, in which:

FIGS. 1A-1C, collectively FIG. 1, illustrate the principle of theStealth Dicing technology;

FIG. 2 displays an increase in net silicon utilization by using smallscribe-lines;

FIGS. 3A-3G show a possible process flow for dicing a wafer according tothe teachings disclosed herein;

FIGS. 3H-31 show two possible alternative actions within the possibleprocess flow for dicing a wafer;

FIGS. 4A-4F, collectively FIG. 4, show a partial process flow for theStealth Dicing and expansion actions;

FIG. 5 shows a cross section through a kerf region of a wafer accordingto another embodiment of the teachings disclosed herein; and

FIG. 6 shows a partial perspective view of a semiconductor devicesingulated using the method of dicing according to the teachingsdisclosed herein.

Before embodiments of the present invention are explained in more detailbelow with reference to the drawings, it is to be noted that equalelements, or those operating in an equal way are provided with same orsimilar reference numerals and figures, and that a repeated descriptionof these elements is omitted.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 shows an explanation of the Stealth Dicing tool and process thatmay be used in the context of the teachings disclosed in this document.

FIG. 1A shows how a laser beam may be focused by means of a focusinglens so that the focal point is at a selected depth within the bulk of asilicon wafer. The laser beam may be moved across the silicon wafer toform an elongated modified wafer region. In FIG. 1A the laser is movedfrom the left to the right as indicated by the dotted arrow. Thus, themodified wafer region has been created to the left of the focal point ofthe laser beam and is about to be created to the right of the focalpoint of the laser beam. The laser may be operated in a continuousmanner, but typically the laser is pulsed so that short laser pulsesinteract with the silicon of the wafer in the vicinity of the focalpoint. An inset to the right in FIG. 1A shows a laser scan surfaceresulting from focusing the laser beam at the selectable depth withinthe bulk of the silicon wafer and moving the laser beam in the indicateddirection (arrow labeled “LASER scan”). It can be seen that a relativelywell-defined modified region can be obtained while the surroundingsilicon material is substantially unaltered.

FIG. 1B shows a top view of an intersection of two scribe-lines or kerfsbefore and after expanding the wafer.

FIG. 1C shows a schematic cross-section through a kerf region after thewafer has been expanded. The saw street or scribe-line width (w) can beempirically estimated with the formula w=0.30×(Wafer thickness) tow=0.40×(Wafer thickness). Therefore, if a wafer, as thick as 300 μm,needs to be Stealth diced by irradiating it from the top surface, w hasto be in the range of 90-120 μm. In order to avoid undesired refractionor reflection of a laser beam, this minimum width (w) has to be keptnormally free from materials other than silicon/silicon dioxide.

Focusing the laser beam into the silicon wafer predetermines a breakingline. The actual singulation is then caused by subsequent tape expansionsupported by a breaking tool. Multiple passes of the laser beam focusedat different depths within the bulk of the wafer will induce awell-controlled and accurately positioned stack of stress-lines one ontop of the other.

In FIG. 2 a graph is provided which shows, as a function of chip area(i.e., the area of one individual chip after singulation), the increasein the number of chips per wafer by reducing the horizontal and verticaldistance between adjacent integrated circuits or chips from a currentreference value of 62 μm to a proposed width of 2 μm. The horizontal andvertical distance is also called “kerf width”. The benefit of reducingthe kerf width to 2 μm is most noticeable for small chip areas, such asa chip area of 0.1225 mm² or 0.16 mm². Using a wafer of 200 mm diameter,over 200,000 chips with a chip area of 1.1225 mm² can be obtained when akerf width of 2 μm is used. This is about 30% more than the number ofchips that can be obtained from the same wafer when a kerf width of 62μm is used. The abbreviation CPW in FIG. 2 means “chips per wafer”.

Embodiments of the teachings disclosed herein may make use of anadditional lithography masking layer. This additional photolithographymasking layer is named KE mask (KE=kerf etch).

According to one aspect of the teachings disclosed herein, a utilizationof a wet etching process of metals is executed in a first part of dicingthe wafer. Briefly, the following steps may be performed in the contextof this aspect of the teachings disclosed herein.

During the manufacturing process of a wafer, a stack of metal (or otherconducting materials) layers is constructed, wherein the stack of metallayers may be shaped as lines around the chip edges and (vertically)connected to each other by appropriate via-contacts. The via-contactscan, e.g., be shaped as slits. As a result, a continuous layer stack ofmetals that is as wide as the KE mask opening or as wide as thekerf-line can be constructed with the resulting stack of metal linesbeing aligned to the KE mask. An oxide plasma etch removes the lastprotective oxide or nitride layer (e.g., a passivation layer) andexposes the top metal layer. A wet etch based on, for example, hydrogenperoxide, sulfuric acid and water (called Piranha) can selectively etchaway the photoresist (comprising, e.g., an organic material) as well asthe stack of metal layers. Such metals can be aluminum, copper ortungsten. Finally, a slit as wide as the KE mask opening will result andthe slit separates the chips from the wafer (silicon) surface.

A dry plasma etch of the single crystal silicon wafer (substrate) isthen performed, which etches a slit around the integrated circuit chipin the silicon. For this etching step an anisotropic etching can be usedso that neighboring circuits in the wafer remain intact.

The wafer is then irradiated by means of a laser beam, for example, fromthe backside. The laser beam is focused at a selectable depth within thebulk of the substrate to form a modified substrate region in thevicinity of the focal point.

The wafer may then be expanded using an expander in order to finalizethe singulation process.

By employing the Stealth Dicing technique, which makes use of a speciallaser beam, in combination with wet and dry plasma etching processingsteps, the teachings disclosed herein seek to solve the problem ofsingulating the integrated circuits manufactured on semiconductor waferswhich are separated by a very small distance (<2 μm). In this way, thepossible number of chips-per-wafer (CPW) and the surface utilization ofthe semiconductor wafers are both increased. As a consequence, the wafermanufacturing costs of the integrated circuits (chips) are reduced.

It has to be pointed out that in reducing the kerf width to the 2 μm,the test and monitor structures normally placed into the kerf can now berearranged and placed, for example, into a space of one or more chips inthe floor plan of the wafer, which is particularly economical for smallchip sizes.

As another option to further reduce the distance separating any twointegrated circuits on a wafer from, for example, 62 μm (in case of akerf designed for mechanical blade dicing) to a much smaller value of ≦2μm, the teachings disclosed herein propose the following solution.

During the manufacturing process of a wafer, a stack of metal layersshaped as lines of widths W (approximately 2 μm) around the chip edgesand connected to each other by appropriate “via-bar” contacts isconstructed. The “via-bar” contacts may actually be shaped as slits. Asa result, a continuous stack of metals is constructed as wide as W(approximately 2 μm).

A dedicated lithography mask, named here KE (Kerf Etch) is aligned tothis stack of metal lines. An oxide plasma etch removes the lastprotective oxide/nitride layer and exposes the top metal layer.

A wet etch based on hydrogen peroxide, sulfuric acid and deionized water(called Piranha) is applied to selectively etch away the organicphotoresist as well as the stack of metals. Such metals are normallyaluminum, copper, or tungsten, or alloys such as TiN, TaN and similar.As a result, a deep slit, as wide as the KE mask opening, will resultwhich separates the chips from above the wafer silicon surface.

A dry plasma etch of the single crystal silicon wafer is then performedwhich etches a slit (also known as trench) around the integratedcircuit.

The Stealth Laser dicing is applied from the backside of the wafer. Aninfrared camera of the Stealth Dicing tool will be capable to align thepositioning of the laser beam(s) to the bottom of the slit/trench.

Hence, an aspect of the teachings disclosed herein makes use of thelaser Stealth Dicing technique, applied from the backside of the wafersubstrate, in combination with a wet etch of a metal stack followed by adry plasma etch of the wafer substrate. The metal stack width can bemade as narrow as 2 μm and below.

The proposed arrangement of established wafer semiconductormanufacturing technologies in conjunction with a new laser-assisteddicing technology can allow the singulation of integrated circuits,which are separated from each other by a very small distance (≦2 μm).

The proposed embodiment is based on a unique utilization of the wet etchof metals to execute the first of a 3-step cut between chips. The secondstep comprises a utilization of a dry plasma etch to etch into the wafersubstrate. The third step is based on the utilization of the StealthLaser dicing technology, typically from the backside of the wafer.

The relatively low costs of the used processes allow the economicalimplementation of a narrow scribe-line or kerf width which leads tolower chip manufacturing costs.

FIGS. 3A-31 show steps of a process flow of dicing a wafer 110 inaccordance with an embodiment of the teachings disclosed in thisdocument. Before the process steps are outlined, the wafer 110 isdescribed in more detail with respect to FIG. 3A.

During the so-called BEOL processing steps, intended to build themetallization structures which connect the electrical nodes of theintegrated circuit, a suitable stack of the same metals is constructed(named Metal Stack Kerf). Such stack of metals can be formed by makinguse of typical via-bar slits filled with the metals, exactly as the restof the metallization and interconnect lines are built within the chip120 a, 120 b. The metal stack has to be located just around all thesides of the chips and the region where the separation of the chips hasto be performed.

FIG. 3A shows a cross-section through the wafer 110. The cross-sectiongoes through a first chip 120 a and a second chip 120 b. In FIG. 3A thefirst chip 120 a is shown on the left-hand side and the second chip 120b is shown on the right hand side, wherein both chips are separated by avertical kerf line region 132 a. The wafer 110 comprises a substrate 210with a first surface 212 and a second surface 214, wherein a layer stack220 is formed on the first surface 212. The layer stack 220 comprises anassembly of layers of alternating first material 222 and a secondmaterial 224. The first material 222 comprises, for example, siliconoxide, and the second material 224 comprises, for example, a nitride.Along the layers of the second material 224 levels for metallizationsare formed as metal layers M1, . . . , M6, which are separated by thefirst material 222. Each of the metal layers M1, . . . , M6 comprisedifferent parts (a plurality of components) formed at laterallydifferent places along the layer stack 220. For example, a first part ofthe first metal layer M1 a is formed at the first chip 120 a and asecond part of the first metal layer M1 b is formed at the second chip120 b, etc. The metal layers M1, M2, . . . , M6 can moreover beconnected by via-contacts V1, V2, . . . , V5. For example, thevia-contact V2 a connects the metal layers M1 a with M2 a (in the firstchip 120 a). The first metal layer M1 can be connected to the substrate210 by contact plugs CP. In the layer stack, the number ofmetallizations may be 1, 2, 3, 4, 5, 6, or more. The number of vialayers is typically one less the number of metallizations.

In the embodiment as shown in FIG. 3A, there are six layers with thefirst material 222 separated by five layers with the second material224. When viewed from the first surface 212 of the substrate 210, thelast layer in the layer assembly 220 comprises an isolation layer 226and a further isolation layer 225 which comprise, for example, a siliconoxide and a nitride. The combination of the isolation layer 226 and thefurther isolation layer 225 may serve as a final passivation of thewafer 210 and the layer stack 220. Of course, other numbers of layers222, 224 may be used as well, and the sequence of the layers may bevaried to the extent that more than two types of materials are arrangedone upon the other. Accordingly, although in the following the number Nof layers Mi 0<i<N is assumed to be 6, other numbers may be used aswell. The substrate 210 comprises a first device 230 a arranged in thefirst chip 120 a and a second device 230 b arranged in the second chip120 b. The first and the second device 230 a and 230 b can, for example,comprise a transistor with doped regions in the substrate 210(comprising, for example, silicon). The first device 230 a can beconnected to the metal layer M1 a by a first contact plug 232 a and thesecond device 230 b can be connected to the metal layer M1 b by a secondcontact plug 232 b. The metal layers M1 a and M1 b are in turn connectedto the metal layers M2 a, M3 a, . . . , M6 a and M1 b, M2 b, . . . , M6b by the via-contacts V1 a, . . . , V5 a and by V lb, . . . , V5 b. Thefirst chip 120 a is sealed by a first seal ring 160 a and the secondchip 120 b is sealed by a second seal ring 160 b, wherein the first andsecond seal rings 160 a and 160 b each comprises two components of themetal layers M1, M2, . . . , M6, which are connected by two componentsof the via-contacts V1, V2, . . . , V5.

The seal rings 160 a, 160 b may be relatively small, for example,between 2 and 8 μm wide, preferably between 4 and 6 μm wide orapproximately 5 μm wide. By comparison, the seal rings are between 20and 30 μm wide in current semiconductor wafer structures.

In more detail, the metal layers Mi=(M1, M2, M3, . . . , M6) comprise aplurality of components Mia, Mib, Mic, Mid, Mie and Mif (the indexi=1,2, . . . ,6 counts the different levels). The metal layers Mia arearranged at the first chip 120 a, the metal layer Mib are arranged atthe second chip 120 b, the third and fourth metal layers Mic and Mid arearranged at the first seal ring 160 a and the metal layer Mie and Mifare arranged at the second seal ring 160 b. The metal layers Mi areconnected by the via-contacts Vi, wherein the component Via of thevia-contacts Vi contact the metal layers Mia at the first chip 120 a,the via-contacts Vib connect the metal layers Mib at the second chip 120b, the via-contacts Vic and Vid connect the metal layers Mic and Mid atthe first seal ring 160 a. The via-contacts Vie and Vif connect themetal layer Mie and Mif at the second seal ring 160 b. In this way, thefirst surface 212 is connected with the last metal layer M6, which inturn is separated from the isolation layer 226 by a last part of thefirst material 222 (i.e., the further isolation layer 225).

Possible materials for the metal layers M1, M2, . . . , M5 comprisealuminum or copper, the metal layer M6 can comprise aluminum, thevia-contacts V1, V2, . . . , V6 can comprise aluminum or copper. Thevia-contact V5 and the contact plugs CP can comprise tungsten. These areexemplary materials and other embodiments may comprise differentmaterials. In addition, the numbers of layers as well as the number ofmetallizations differ in other embodiments.

In the situation depicted in FIG. 3A, the chips formed within thesubstrate 210, the stack 220 and isolation or passivation layer 226, 225may be completely processed in that these chips merely need to be dicedand no further processing regarding the schematics of a circuitry of thechips is necessary. Some portions of the upper metal layer M6 may formor may be contacted with contact pads, the contact pads not being shownin FIG. 3A in order to ease the understanding of FIG. 3A and thesubsequent figures. The contact pads allow for an external contact ofthe circuitry of the chips and are left uncovered by the isolation layer226 which otherwise overlays all chip areas.

Along the vertical kerf-line region 132 a, the layer stack 220 comprisesconducting materials from the first surface 212 to the last metal layerlevel M6. Hence, the kerf-line region 132 a comprises a layer stackbeing formed, e.g., by a plurality of metal layers along the metallayers M1, M2, M3, . . . , M6, which in turn can be connected byvia-contacts V1, V2, . . . , V5. On the last metal level M6, there aretwo isolation layers 225 and 226, which again protect the wafer 110. Onthe other side, a contact plug CP connects the first metal level M1 withthe substrate 210.

A possible material of the six level M6 of metal layers is aluminum, thevia-contacts V5 and the contact plug CP between the first metallic layerM1 and the substrate 210 can, for example, comprise tungsten and thematerial of the metal levels M1 to M5 as well as the via-contacts V1-V4can, for example, comprise aluminum or copper.

After explaining the structure of the wafer, the actions of dicing aredescribed next. In a first action of dicing the wafer 110, a KE resistlayer 310 (see FIG. 3B) is deposited on the isolation layer 226. The KEresist layer 310 can, for example, comprise an organic material and ispatterned by using a KE mask. In particular, the following actions maybe performed. Forming a photoresist layer (KE) and performing aphotolithographic process to selectively remove a photoresist KE abovethe Metal Stack Kerf.

FIG. 3B shows a result of patterning of the KE resist layer 310 with afirst part 310 a and a second part 310 b, which are separated by anopening 320 due to the patterning. The opening 320 is positioned alongthe vertical kerf-line 132 a (which continues in the directionperpendicular to the drawing plane). The first part 310 a of the KEresist layer is therefore formed on the first chip 120 a with the firstseal ring 160 a, the second part of the KE resist layer 310 b is formedon the second chip 120 b with the second seal ring 160 b, and along theopening 320, the isolation layer 226 is exposed. After the exposure ofthe isolation layer 226, a development can be performed to the first andsecond parts of the KE resist layers 310 a, 310 b. The patterning of theKE resist layer 310 can, for example, comprise an etching step.

In FIG. 3C an action of selective etching is (or has been) performed inorder to remove the isolation layer 226 and the further isolation layer225 which comprise, for example, a silicon oxide and a nitride. As aconsequence, the sixth level of metal layers M6 is exposed along theopening 320. In other words, a dry plasma etch (or, alternatively a wetchemical etch) may be performed to remove the final passivationdielectric layer(s) above the Metal Stack Kerf.

After the KE etch of the top oxide nitride layer, FIG. 3D shows an etchaction in which the conducting material along the layer stack 220 isremoved from the opening 320 to the first surface 212 of the substrate210. Therefore, along the vertical kerf-line region 132 a, the layerstack 220 of the first chip 120 a with the first seal ring 160 a isseparated from the layer stack 220 of the second chip 120 b with thesecond seal ring 160 b. The step of removing the conducting materialsalong the vertical kerf-line region 132 a can, for example, comprise anetching step, which selectively etches the metallic layers M6-M1, thevia-contact V1-V5 and the contact plug CP, e.g., on the substrate 210.During this etching action, the substrate 210 can also be etched to acertain degree (not shown in this figure), so that also part of thesubstrate 210 is removed during this step.

The action of removing the conducting materials can, for example,comprise the KE kerf etch, wet etch, which is based, for example, on achemical solution called Piranha, which selectively removes organicphotoresists as well as metallics. Naturally, other chemical solutionsmay be applicable as well. At the time when the conducting materialinside the opening 320 along the vertical kerf-line region 132 a isremoved, the KE resist layer 310 (or their parts 310 a, 310 b, etc.) canalso be removed. This is possible by appropriately choosing the chemicalsolution.

FIG. 3E shows a step in which a part 326 of the substrate 210 isremoved, for example to a depth D which is, for example, smaller thanthe thickness L of the substrate 210. FIG. 3E also shows that during theetching step, which removes the metallic layers inside the layer stack220, also a small amount of thickness AD of the substrate 210 isremoved. This step can comprise an anisotropic etching which removessubstrate material only along the vertical kerf-line region 132 a, andcan comprise a plasma etching step. Accordingly, the following actionsmay be carried out. Perform a wet chemical etch (based on a suitablesolution of water-sulfuric acid-hydrogen peroxide, generally denoted asPiranha) to remove the photoresist and as well a full Metal Stack Kerf.Piranha is selective to silicon oxide and silicone nitride. As a result,the wafer substrate will be exposed. In other words, while the entiremetal stack or pillar is removed, the surrounding oxide is not or onlynegligible affected by the wet etching process.

The trench structure may have a depth D of 10 to 50 μm, preferably 15 to40 μm, and more preferably of 20 to 30 μm. The trench structure maytypically have a minimum depth of 1 μm.

With a depth D of the trench structure of at least 10 μm, the modifiedsubstrate regions generated during the Stealth Dicing action aresufficiently far away from electronic structures 230 a, 230 b, such astransistors, diodes, etc. that are typically found in the chips 120 a,120 b. In this manner, virtually no modification of the electricalproperties of the semiconductor devices 230 a, 230 b will occur duringthe action of irradiating the substrate with the laser beam.

The stack of metals that is etched away to perform the trench structurecan be positioned with the same precision as the semiconductorstructures created in the chips 120 a, 120 b. During the action ofirradiating the substrate with a laser beam, as will be explained belowwith respect to FIG. 3H or FIG. 3I, a camera may see the presence of thetrenches or slits which are on a lower surface. In this manner, a highlyprecise positioning of the Stealth Dicing tool can be obtained.

FIG. 3E also shows the result of a plasma dry etch of the wafersubstrate to form a trench slit around each chip.

FIG. 3F shows the result of an ensuing thinning process of the wafer 210from the second surface 214, so that the substrate comprises a thicknessL′ which is, in general, larger than the depth D of the part 326 of thesubstrate 210 removed in the previous step. This thinning process toreduce the thickness of the substrate 210 from an initial value L to asmaller value L′ is optional. Hence, a wafer backside grinding isperformed to reduce the wafer substrate thickness to the needed value(optional step).

FIG. 3G shows an action of the wafer dicing process in which a laserbackside Stealth Dicing is performed. A laser source 380 creates a laserbeam that is focused to a depth within the substrate 210 between abottom of the part 326 which forms a trench structure and the secondmain surface 214. The second main surface 214 is typically opposite tothe first main surface 212. Note that depending on whether the optionalgrinding action shown in FIG. 3F has been performed or not, the distancebetween the first main surface 212 and the second main surface 214 maybe either the original value L or the reduced value L′.

The laser beam focused at the substrate region between the trenchstructure 326 and the second main surface 214 may locally modify thesubstrate material in the vicinity of the focal point if the power ofthe laser beam is in a certain power range. In particular, the laserbeam may modify the substrate material by converting the initiallymono-crystalline substrate material to a poly-crystalline structure.FIG. 3G shows two modified regions 381 obtained by focusing the laserbeam at two different depths within the bulk of the substrate 210. Asingle modified region 381 could also be employed, or a number ofmodified regions larger than two. Typically, the modified region 381 isline-shaped in the direction perpendicular to the drawing plane of FIG.3G.

A Stealth Dicing tool used to perform the action of laser backsideStealth Dicing may comprise alignment features that are typicallyassisted by an infrared camera. The alignment features of the StealthDicing tool will be able to align the laser shooting to the bottom ofthe trench structure 326 formed in the action illustrated in FIG. 3F.

The stack of metals that is etched away to perform the trench structurecan be positioned with the same precision as the semiconductorstructures created in the chips 120 a, 120 b. During the action ofirradiating the substrate with a laser beam, a camera may see thepresence of the trenches or slits which are on a lower surface. In thismanner, a highly precise positioning of the Stealth Dicing tool can beobtained.

The chips shall be singulated once processed through the expander moduleof the Stealth Dicing tool, as will be explained in the context of thedescription of FIG. 4.

As an alternative to the actions corresponding to FIGS. 3F and 3G, theactions illustrated in FIGS. 3H and 31 may be performed. Instead ofperforming a plasma dry etch of the wafer substrate 210 to form a trenchslit around each chip, a wet chemical etch (based on a suitable KOHsolution) may be performed. Due to anisotropic etching properties of theKOH solution, the resulting trench slit 327 will have a V-shapedprofile. The result of the wet chemical etch is shown in FIG. 3H. Atypical ratio between the width W and the depth D of the V-shapedprofile may be D=0.7 W.

The action illustrated in FIG. 31 corresponds by and large to the actionillustrated in FIG. 3G. The laser source 380 produces a laser beamfocused at a depth within the bulk of the substrate 210 between thetrench structure 327 and the second main surface 214 of the substrate210. Two modified substrate regions 381 are illustrated in FIG. 31,which are vertically aligned to the tip of the trench structure 327.Note that the size of the modified regions 381 is not necessary to scalewith, for example, the width W of the trench structure 327. For example,the modified regions 381 could be as wide or even wider than the width Wof the trench structure 327.

According to some embodiments of the teachings disclosed here, acontinuous portion, which may be either metal or a dielectric material,is defined around each chip, i.e., along the scribe-lines. Thiscontinuous portion is then etched by means of a selective etchingprocess, so that any surrounding material is not or only negligiblyaffected by the selective etching process. When the etching processreaches the first main surface of the substrate, an over-etch isperformed to form a trench. In the alternative, another etching processmay be used which etches especially the substrate material. A subsequentStealth Dicing action is typically performed from the backside of thesubstrate, i.e., from the side of the second main surface 214. However,the Stealth Dicing could also be performed from the front side of thewafer.

FIG. 4 illustrates a number of actions performed during a second part ofthe wafer dicing process according to the teachings disclosed herein.The actions illustrated in FIG. 4 begin after all etching actions havebeen performed on the wafer, i.e., either subsequent to the stateillustrated in FIG. 3F or subsequent to the state illustrated in FIG.3H.

In FIG. 4A the wafer 110 is mounted to a wafer mounter 410. In theexample shown in FIG. 4, the wafer 110 is an 8″ wafer. The wafer mounter410 is fixed to an 8″ frame 412.

FIG. 4B corresponds to FIGS. 3G or 31. The wafer 110 which is placedupside down on the wafer mounter 410 undergoes a Stealth Dicingoperation using the laser source 380. Note that at this stage the wafer110 is not yet actually singulated, but only weakened at the intendeddicing location due to the Stealth Dicing action and the previouslyformed trench structures.

The actual singulation is performed during an action illustrated in FIG.4C. The wafer mounter 410 is expanded by means of a clamp ring 413, abreaking tool 414 may be slid across the lower surface of the wafermounter 410 which is opposite to the surface where the wafer 110 isplaced. The breaking tool 414 locally deflect the wafer mounter 410 andthe wafer 110 which causes the wafer 110 to break at the intendedsingulation locations, if breaking has not yet occurred due to theextension of the wafer mounter 410. The actions shown in FIG. 4C resultin individual, singulated chips 120 a, 120 b.

Depending on the desired package or shipping of the individual,singulated chips 120 a, 120 b, etc., different options exist forhandling the chips 120 a, 120 b, . . . .

FIG. 4 illustrates two of these options. A first option is shown in FIG.4D. While still being on the wafer mounter 410, the singulated chips areirradiated with ultraviolet light. When the wafer is placed on themounter (FIG. 4A), it may be held by a special adhesive tape which hasthe property to highly reduce its adhesion strength when irradiated by asuitable dose of ultraviolet (UV) energy. In a subsequent step shown inFIG. 4E the individual, singulated chips are processed by a die bonder.The die bonder is the tool that picks the singulated chips and executesthe wire bonding process.

Another option illustrated in FIG. 4F consists in remounting thesingulated chips 120 a, 120 b to another support 415 from which they maybe picked during an assembly of electronic devices, for example.

The wafer dicing process described herein results in a high dicingquality. To mention the most important figures of merit: very sharp chipsidewalls, virtually no cracks, virtually no chipping, virtually no padcorrosion, no wafer dust on chip surface, virtually no delamination ofthe top layers of the chip.

In contrast to mechanical blade dicing, the singulation process is notlimited to squared or rectangular chip shapes or to rectangularsingulation lines extending across the entire wafer. Instead, chips ofall shapes can be singulated, especially if the Stealth Dicing tool wasmodified to support arbitrary shapes of the singulation lines.

A high utilization percentage of wafer area is achieved, especially whenthe kerf width is reduced to ≦2 μm.

Since no critical dimensional control is required to perform the neededwafer manufacturing operations once the etching is finished, one benefitof the teachings disclosed herein consists in the fact that thenecessary tools do not need to be particularly advanced (at least, withrespect to the current technological status). The tools could be fullydepreciated, therefore minimizing the manufacturing costs of theoperations.

The classical dicing tools based on high-speed rotating blades are notneeded any longer. They may be replaced with the Stealth Laser dicingtools.

Due to the presence of the deep trench, the dicing speed of the StealthDicing tool is higher than in a case without a trench (less laser pulsepasses are needed).

Due to the presence of the trench, the separation line between chips atthe wafer surface is much more precise than in the case without a trench(especially in the case of rotated silicon wafers).

FIG. 5 shows a cross-section of a wafer 110 similar to the cross-sectionof the wafer shown in FIG. 3A. However, in comparison to the structureshown in FIG. 3A, the total kerf width is further reduced by omittingthe seal rings 160 a, 160 b. As mentioned above, it is possible toobtain very sharp chip sidewalls and the risk of cracking, chipping, padcorrosion or de-lamination of the top layers of the chip issubstantially reduced. Instead of omitting the seal rings 160 a, 160 bcompletely, it may also be possible to reduce the lateral dimension ofthe seal rings, for example, to half of the size of the seal rings 160a, 160 b, shown in FIG. 3A.

FIG. 6 shows a partial perspective view of a singulated semiconductordevice obtained using a waver dicing method according to the teachingsdisclosed herein. The semiconductor device comprises the substrate 210and the layer stack 220. On the upper main surface of the layer stack220, a number of structures are schematically represented that are notfurther specified. For example, these structures could be connectionpads. At the lateral surface or side surface of the substrate, tworegions can be observed. An upper region corresponds to the removed part326 obtained during the etching of the substrate 210. In accordance withFIG. 3E, this region has a height of D (or D+ΔD, to be more precise).

A second region of the sidewall of the semiconductor device is locatedbetween a bottom of the former trench structure 326 and a second mainsurface 214 of the substrate 210. The former bottom of the trenchstructure 326 might still be observable as a small pedestal; however,this is not necessarily the case. The second region of the sidewall ofthe substrate 210 comprises one or more modified substrate regions 381in the form of lines on the side surface extending in directionsparallel to the first and second main surfaces 212, 214. The modifiedsubstrate region 381 may be viewable as lines of stress generated by theStealth Laser pulses using a conventional microscope or an electronmicroscope.

The upper region of the sidewall of the substrate 210 corresponding tothe former trench structure 326 is substantially flush with a sidewallof the layer stack 220.

The Stealth Laser pulses typically leave a clear sign of theirapplication as proven by the presence of darker and rougher linesvisible by inspecting the edges of singulated chips using, e.g., anelectron microscope. Furthermore, the sharpness of the edges of thechips is a sign that no classical mechanical sawing (blade dicing) hasbeen utilized.

An inspection of the sides of the chip from the upper silicon face downfor a few micron may typically reveal a very smooth surface, sign of thedry plasma trench etch.

An inspection of back-end-of-line stack may typically reveal a kind ofzigzag profile, sign of the original presence of the Metal Stack Kerf(see, for example, FIG. 3D).

Therefore, by means of suitable decapsulation techniques, it may bepossible to determine if the Stealth Laser dicing in conjunction with aMetal Stack Kerf and Silicon Plasma Trench etch has been applied.

The method of dicing a semiconductor wafer according to the teachingsdisclosed herein may be used by semiconductor manufacturing companies,such as foundries and integrated device manufacturers (IDM). Inparticular, the teachings disclosed herein may be used for productswhose area is less than approximately 3×3 mm², products/chips ofdifferent sizes arranged in an irregular matrix on shared reticles, orproducts requiring particular dicing quality. A method of dicing asemiconductor wafer according to the teachings disclosed herein may beparticularly economically convenient for small area products, i.e., lessthan approximately 3×3 mm² mentioned above. The size of the chips maybe, for example, 1 mm², 0.25 mm², 0.16 mm², or 0.1225 mm², for example.Using the teachings disclosed herein, the individual chip may bepositioned closely to each other on the wafer 110.

Although some aspects have been described in the context of anapparatus, it is clear that these aspects also represent a descriptionof the corresponding method, where a block or device corresponds to amethod step or a feature of a method step. Analogously, aspectsdescribed in the context of a method step also represent a descriptionof a corresponding block or item or feature of a correspondingapparatus. Some or all of the method steps may be executed by (or using)a hardware apparatus, like for example, a microprocessor, a programmablecomputer or an electronic circuit. In some embodiments, some, one ormore of the most important method steps may be executed by such anapparatus.

The above described embodiments are merely illustrative for theprinciples of the present invention. It is understood that modificationsand variations of the arrangements and the details described herein willbe apparent to others skilled in the art. It is the intent, therefore,to be limited only by the scope of the impending patent claims and notby the specific details presented by way of description and explanationof the embodiments herein.

What is claimed is:
 1. A method of dicing a semiconductor wafer, themethod comprising: forming a layer stack on a first main surface of asubstrate; etching the layer stack and a portion of the substrateaccording to a pattern defining an intended dicing location to obtain atrench structure; and irradiating the substrate with a laser beam tolocally modify the substrate between a bottom of the trench structureand a second main surface of the substrate opposite to the first mainsurface.
 2. The method of claim 1, wherein forming the layer stackcomprises: forming an interconnection layer comprising a metal region atthe intended dicing location; and forming a via layer adjacent to theinterconnection layer, the via layer comprising a metallic via bar atthe intended dicing location contacting the metal region of theinterconnection layer.
 3. The method of claim 2, wherein the metallicvia bar is shaped as a slit.
 4. The method of claim 2, wherein the metalregion and the metallic via bar form at least one loop to laterallyenclose at least one chip region of the semiconductor wafer.
 5. Themethod of claim 1, further comprising: aligning a lithography maskdefining the intended dicing location on a protective oxide/nitridelayer that is a top layer of the layer stack; and removing theprotective oxide/nitride layer using a dry plasma etch or a wet chemicaletch to expose a metal layer of the layer stack beneath the protectiveoxide/nitride layer.
 6. The method of claim 1, wherein etching the layerstack is performed using a wet etch.
 7. The method of claim 6, whereinthe wet etch is based on at least one of hydrogen peroxide, sulfuricacid, and/or de-ionized water.
 8. The method of claim 1, wherein etchingthe substrate is performed using a dry plasma etch or a wet chemicaletch.
 9. The method of claim 1, wherein irradiating the substrate withthe laser beam is performed from the second main surface of thesubstrate.
 10. The method of claim 1, further comprising: aligning alaser source to the intended dicing location using an infrared cameraprior to irradiating the substrate, the laser beam emanating from thelaser source.
 11. The method of claim 1, wherein etching the layer stackand the portion of the substrate produces the trench structure having awidth of 10 μm or less.
 12. The method of claim 1, wherein etching theportion of the substrate is performed to a depth of 1 μm or more. 13.The method of claim 1, wherein forming the layer stack is performedduring a back-end-of-line process of a semiconductor manufacturingprocess.
 14. The method of claim 1, further comprising: performing awafer backside grinding prior to irradiating.
 15. The method of claim 1,further comprising, subsequent to irradiating the substrate: singulatinga plurality of chip elements formed on the semiconductor wafer using anexpander comprising an expandable surface on which the wafer is placed.16. The method of claim 1, wherein irradiating the substrate comprisingfocusing the laser beam at a depth within the substrate and moving thelaser beam along the intended dicing location.
 17. The method of claim1, wherein irradiating the substrate comprises focusing the laser beamsuccessively at a plurality of depths within the substrate to obtain adistributed or enlarged modified substrate region.
 18. The method ofclaim 1, wherein irradiating the substrate produces a modified substrateregion having a poly-crystalline morphology and/or an amorphousmorphology.
 19. A method of dicing a semiconductor wafer, the methodcomprising: defining a continuous portion of metal or a dielectricaround a chip in a layer stack on a first main surface of a substrate;etching the continuous portion to obtain an upper portion of a trenchstructure; etching the substrate at locations exposed by the upperportion of the trench structure to obtain a lower portion of the trenchstructure; and irradiating the substrate with a laser beam focused at aregion between the lower portion of the trench structure and a secondmain surface of the substrate opposite to the first main surface.
 20. Amethod of dicing a semiconductor wafer, the method comprising: forming alayer stack on a first main surface of a substrate, the layer stackcomprising a final passivation layer and a metal region at an intendedlateral dicing location; forming a photoresist layer on the finalpassivation layer; performing a photolithographic process to selectivelyremove the photoresist layer at a location that is substantially alignedto the metal region; etching the final passivation layer at the locationthat is substantially aligned to the metal region due to thephotolithographic process; etching the metal region of the layer stackto expose the first main surface of the substrate at the intendedlateral dicing location; etching the substrate through an opening in thelayer stack obtained during the etching of the metal region to obtain atrench structure in the substrate; irradiating the substrate with alaser beam to locally modify the substrate between a bottom of thetrench structure and a second main surface of the substrate opposite tothe first main surface; and singulating individual chips.